The invention relates to an output driver for integrated circuits and a method for controlling the output impedance of an integrated circuit.
Output drivers are important building blocks in the input/output (I/O) path of integrated circuits like microprocessors and memory systems. They act as the primary interface through which data transmission takes place between the integrated circuit and external systems via transmission lines. For this end, the output driver has to convert the chip-internal logic levels and noise margins to those required for driving the inputs of chip-external circuits in digital systems.
The operation of the output driver of an integrated circuit in certain temperature and supply voltage ranges have to satisfy requirements in both DC and AC conditions, which are specified at the outset of design. The AC operating conditions for the outputs determine the properties of the signal-transients which are to be performed by the output drivers at given DC signal levels, and include the required rise time tr and fall time tf of the output signal when the data output is connected to a specific load impedance. Thus, in order to avoid undesired degradations of the output data, the output impedance of the output driver has to be properly matched to the characteristic impedance of the transmission line connecting the data output to the chip-external system.
For lossless transmission lines which are terminated by purely ohmic impedances (ZL=R), the voltage reflection coefficient xcfx81v is given by xcfx81v=(Rxe2x88x92Z0)/(R+Z0) wherein Z0 is the characteristic wave impedance of the transmission line. Therefore, if the characteristic impedance of the transmission line Z0 matches the output impedance of the output driver, no signal reflection occurs and xcfx81v=0.
The characteristic impedance of the transmission may have a slight temperature dependency. Furthermore, the channel resistances of the n- and p-MOS transistors of the output driver will vary with the (manufacturing) process (P), the operating voltage (V) and the operating temperature (T). In order to minimize or avoid impedance mismatches caused by such PVT-variations, so called PVT-sensors have been applied in conventional output drivers. These sensors detected PVT changes and, using predetermined impedance correction data, correspondingly adjust the output impedance of the output driver. However, applying PVT-sensors in integrated circuits has severe drawbacks in that they are complicated circuits with limited impedance correction accuracy.
An object of the present invention is to provide an output driver for integrated circuits (such as memory or microprocessor circuits), which allows for a simple and efficient control of the output impedance thereof. It is further an object of the invention to provide a method for controlling the output impedance of an integrated circuit.
These problems are solved by an output driver according to claim 1 and a method according to claim 10, respectively. Preferred embodiments are subject of the dependent claims.
According to the invention an output driver for integrated circuit includes:
at least one driver circuit for driving an external circuit, the driver circuit having
at least one data input connectable to the integrated circuit;
at least one data output connectable to a transmission line leading to the external circuit; and
impedance adjusting means for adjusting the output impedance of the driver circuit according to determinable impedance adjusting data;
at least one dummy circuit comprising a dummy driver circuit and a dummy transmission line, the dummy driver circuit and the dummy transmission line being electrical replica of the driver circuit and of the transmission line, respectively; and
at least one impedance control circuit for controlling the output impedance of the driver circuit, the impedance control circuit being connected to the dummy circuit and the impedance adjusting means;
wherein the impedance control circuit is adapted to control the impedance of the driver circuit by determining the impedance adjusting data necessary for matching the output impedance of the dummy driver circuit to the characteristic impedance of the dummy transmission line and outputting the determined impedance adjusting data to the impedance adjusting means of the driver circuit.
Hence, according to one aspect of the invention, the output driver includes an additional xe2x80x9cdummyxe2x80x9d circuit, which is essentially used to determine the impedance adjusting data necessary for matching the output impedance of the driver circuit to the characteristic impedance of the transmission line. This dummy circuit includes a replica of the (actual) driver circuit as well as a replica of the (actual) transmission line. Thus, the actual driver circuit and the actual transmission line are electrically or physically modeled as dummy replica circuits in the output driver. It is to be understood that the dummy circuit does not have a data output connectable to the external circuit, i.e. the dummy transmission line is not connected to the external circuit.
Similarly, the dummy driver circuit also includes electrical replica of the impedance adjusting means. The impedance control circuit uses this dummy circuit to determine which impedance adjusting data, under the present operating voltage and temperature, are necessary for matching the impedances. Since the dummy driver circuit and the dummy transmission line are designed to have the same electrical characteristics as the actual driver circuit and the actual transmission line, the impedance adjusting data thus determined are suitable for an efficient matching of the driver circuit to the transmission line connected thereto. Consequently, a complicated PVT-sensor is not necessary. Instead, changes of the channel resistances of the driver transistors of the driver circuit resulting in changes of the output impedance are detected by the impedance control circuit using the dummy circuit.
Preferably, the dummy driver circuit is a scaled down replica of the driver circuit. The scaling factor might, for example, lie within the range of two to ten. Scaling down the transistor dimensions of the dummy driver circuit relative to those of the driver circuit is favorable, since smaller transistors in the dummy circuit will dissipate less power. Therefore, less heat is generated by the dummy circuit so that such an output driver is also applicable in low-energy applications.
The dummy driver circuit does not need to be an exact replica of the driver circuit in a geometrical sense. Although the dummy driver circuit might be designed to represent an exact geometrical miniature replica of the driver circuit (for example scaled down by the geometrical factor of eight), it is equally possible to use a different (favorably simpler) design for the dummy driver circuit as long as its electrical characteristics closely resemble those of the (actual) driver circuit. Increases of the channel resistances of scaled down transistors in the dummy driver circuit have to be accounted for when determining the impedance adjusting data used for matching the output impedance of the driver circuit. Beneficially, if the transistors in the dummy driver circuit are scaled down by a geometrical scaling factor of k (resulting in an increase of the channel resistances by this factor of k), the dummy transmission line is designed to have a characteristic impedance of k*Z0, wherein Z0 is the characteristic impedance of the actual transmission line. Thus, the impedance of the dummy transmission line is scaled up by k, if the transistors of the dummy driver circuit are scaled down by k.
Favorably, the dummy transmission line includes at least one polysilicon resistor and/or metal resistor. As described above, impedance mismatches between the driver circuit and the transmission line connected thereto can arise due to variations of the electrical characteristics of the transistors of the driver circuit as well as due to variations of the characteristic impedance of the transmission line. Therefore, in order achieve a precise impedance matching, it is favorable to model the electric characteristics of the transmission line within the dummy circuit as closely as possible. The dummy transmission line included within the dummy circuit is designed to be an electrical replica of the (actual) transmission line, which is specified to be used with the integrated circuit. For this end, the dummy transmission line may include polysilicon resistors (gate contact resistors (GC-resistors)) and/or metal resistors. Furthermore, also diffusion resistors and other electrical components may be applied. Favorably, the temperature dependency of the characteristic impedance of the transmission line is also modeled, so that the effects of temperature variations on the characteristic impedance of the transmission line can be accounted for.
According to a preferred embodiment, the impedance adjusting means includes a plurality of impedance adjusting transistors connected in parallel, the gate potentials of the transistors being determined by the impedance adjusting data. Depending on the impedance adjusting data, none, some or all of the impedance adjusting transistors are activated. This parallel circuitry of transistors is used at the output stage of the driver circuit, so that it influences the output impedance thereof. For example, the circuit of parallel impedance adjusting transistors could be connected in parallel or in series to an output driver transistor of the driver circuit.
According to a preferred embodiment, the driver circuit is a push-pull on-chip current driver (PP-OCD). Although the invention is equally applicable to so called open drain on-chip current drivers (OD-OCD), it is particularly favorable for the use within PP-OCD. PP-OCD are a widely used on-chip driver type in memory (especially DRAMs) and other VLSI systems. Such an output driver typically has a tristate output waveform at the date output. When no data is to be transmitted, the data output of a PP-OCD remains at a reference voltage (VREF), which is typically half of the external supply voltage VDD. When a (binary) logic xe2x80x9c1xe2x80x9d is to be transmitted, a push-up circuit of the PP-OCD will be active and the output will be pushed-up from the VREF value by a predetermined amount. Similarly, when a (binary) logic xe2x80x9c0xe2x80x9d is to be transmitted, the output will be pulled-down by the same preset amount.
In order to ensure a proper communication between the PP-OCD and the external world through the transmission line, it is necessary that the output impedance of the both the push-up circuit and the pull-down circuit of the PP-OCD should equal the characteristic impedance Z0 of the transmission line so that the output of the PP-OCD remains at the VREF potential when not data is transmitted. Thus, the PP-OCD has to be operated symmetrically (the so called symmetry of operation for PP-OCD). According to the present invention, the symmetry of operation can be easily achieved and an effective matching of impedances between the output driver and the transmission line is possible.
Favorably, the impedance adjusting means includes:
a first group of p-transistors connected in parallel between a high supply voltage and a push-up circuit of the driver circuit, and
a second group of n-transistors connected in parallel between a low supply voltage and a pull-down circuit of the driver circuit.
Thus, in order to adjust the output impedance of the driver circuit, a plurality of p-transistors can be connected in parallel between a high supply voltage (VDD) and the push-up circuit of the output driver. Therefore, the first group of p-transistors is connected in series between the supply voltage and the push-up circuit. Consequently, depending on the activated number of p-transistors of the first group, the (total) output impedance of the driver circuit for the binary data xe2x80x9c1xe2x80x9d can be adjusted. The same applies for the pull-down circuit used for outputting a logic xe2x80x9c0xe2x80x9d.
Favorably, the first and/or the second group include N of the transistors and the impedance adjusting data are N-bit binary data. The transistors of the first and/or second group do not necessarily have identical design parameters. In a simple embodiment, for example, N different transistors are used. The transistor representing the first bit of the N-bit binary data might have a channel resistance R. The (second) transistor representing the second bit of the N-bit binary data might have a channel resistance of R/21. The (third) transistor representing the third bit of the N-bit binary data might have a channel resistance of R/22=R/4 and so on. Therefore, by applying the N-bit binary data to such a group of parallel transistors, 2N different resistance values can be set. In practice, sufficient results are achieved using four transistors, i.e. 4-bit binary data.
According to a preferred embodiment, the impedance control circuit is adapted to determine and to output the impedance adjusting values at regular intervals. Although it is possible to determine and to output the impedance adjusting data for each clock cycle of the integrated circuit, it is usually sufficient to determine and to output the impedance adjusting data at larger intervals.
Favorably, in case a DRAM-circuit is used as the integrated circuit, the impedance control circuit determines and outputs impedance adjusting data within every refresh cycle. Favorably, the impedance control circuit has an adjusting mode and a preset mode, which are externally selectable. In the adjusting mode of the impedance control circuit, the impedance adjusting data are determined using the dummy circuit. In the preset mode, predetermined impedance adjusting data are outputted to the driver circuit. These predetermined impedance adjusting data represent typical correction values resulting in an acceptable impedance matching under typical operating conditions. Furthermore, the impedance control circuit might also have a test mode, which will help to check the functionality of the impedance control circuit as well as to allow a manual control of the impedance adjusting data from the external world.
According to another preferred embodiment, the impedance control circuit includes an adjusting data generator outputting binary impedance adjusting data to the dummy driver circuit and a comparator comparing the impedance of the dummy driver circuit to the characteristic impedance of the dummy transmission line. In a simplest embodiment, such an adjusting data generator might be a counter. In an adjusting mode of the impedance control circuit, the counter will increment and output binary impedance adjusting data to the dummy circuit. For every impedance adjusting data outputted by the counter, the comparator will compare the voltage drop on the dummy transmission line with a fixed reference voltage. For the impedance adjusting data for which the detected voltage on the dummy transmission line closely equals the reference voltage, the impedance matching is achieved. These impedance adjusting data are subsequently outputted to the driver circuit in order to match the output impedance thereof to the characteristic impedance of the transmission line.
According to the invention, a method for controlling the output impedance of an integrated circuit includes the steps of
proving the integrated circuit comprising at least one driver circuit for driving an external circuit, the driver circuit having
at least one data input connectable to the integrated circuit;
at least one data output connectable to a transmission line leading to the external circuit; and
impedance adjusting means for adjusting the output impedance of the driver circuit according to determinable impedance adjusting data;
determining the impedance adjusting data necessary for matching the output impedance of a dummy driver circuit to the characteristic impedance of a dummy transmission line, the dummy driver circuit and the dummy transmission line being electrical replica of the driver circuit and of the transmission line, respectively; and
outputting the determined impedance adjusting data to the impedance adjusting means of the driver circuit to match the output impedance of the driver circuit to characteristic impedance of the transmission line.
Therefore, unlike conventional methods for controlling the output impedance of integrated circuits, determining the impedance adjusting data involves determining impedance adjusting data suitable for impedance matching of a dummy driver circuit to a dummy transmission line. These dummy circuits are electrical replica of the actual driver circuit and actual transmission line. A complicated sensing of PVT-changes using sensors is not necessary.